2662 search results - page 178 / 533 » Tools Demonstrations |
138
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TASE
2008
IEEE
15 years 4 months ago
2008
IEEE
The safety of pointer programs is an important issue in high-assurance software design, and their verification remains a major challenge. Pointer Logic has been proposed to verify...
137
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FPL
2005
Springer
15 years 10 months ago
2005
Springer
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
128
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CBSE
2009
Springer
15 years 9 months ago
2009
Springer
A challenge of componentizing legacy applications is to extract behavior specification of suggested components. It is desirable to preserve a relation between the original structur...
120
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ECBS
2006
IEEE
15 years 8 months ago
2006
IEEE
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
105
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LREC
2010
15 years 6 months ago
2010
We present our efforts to create a large-scale, semi-automatically annotated parallel corpus of cleft constructions. The corpus is intended to reduce or make more effective the ma...