300 search results - page 5 / 60 » Tools and Methodologies for Low Power Design |
SBCCI
2003
ACM
15 years 2 months ago
2003
ACM
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and h...
108
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ISVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
VLSISP
2008
14 years 8 months ago
2008
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
101
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VLSID
2010
IEEE
15 years 1 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...