Sciweavers

1541 search results - page 19 / 309
» Tools and Techniques for Model Checking Networked Programs
Sort
View
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
16 years 25 days ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
CCR
2004
151views more  CCR 2004»
15 years 9 days ago
Practical verification techniques for wide-area routing
Protocol and system designers use verification techniques to analyze a system's correctness properties. Network operators need verification techniques to ensure the "cor...
Nick Feamster
DAC
1998
ACM
16 years 1 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
EMSOFT
2006
Springer
15 years 2 months ago
Reusable models for timing and liveness analysis of middleware for distributed real-time and embedded systems
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...
Venkita Subramonian, Christopher D. Gill, Cé...
132
Voted
FMICS
2009
Springer
15 years 4 months ago
Platform-Specific Restrictions on Concurrency in Model Checking of Java Programs
The main limitation of software model checking is that, due to state explosion, it does not scale to real-world multi-threaded programs. One of the reasons is that current software...
Pavel Parizek, Tomás Kalibera