This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
This work addresses the question of supporting web designers in considering usability in their work in order to foster user-centered design of web sites. With the MetroWeb tool th...
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
Pawlak recently introduced rough set flow graphs (RSFGs) as a graphical framework for reasoning from data. Each rule is associated with three coefficients, which have been shown t...
We show the universality of the VEDIC network in simulating other well known interconnection networks by generating the parameters of the VEDtC network automatically. Algorithms a...