Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
We present the first thorough theoretical analysis of the Transitivity Editing problem on digraphs. Herein, the task is to perform a minimum number of arc insertions or deletions ...
Mathias Weller, Christian Komusiewicz, Rolf Nieder...
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
—This paper presents a systematic in-depth study on the existence, importance, and application of stable nodes in peerto-peer live video streaming. Using traces from a real large...