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» Total power-optimal pipelining and parallel processing under...
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65
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ICCAD
2005
IEEE
84views Hardware» more  ICCAD 2005»
15 years 3 months ago
Total power-optimal pipelining and parallel processing under process variations in nanometer technology
Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek D...
80
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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
15 years 10 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
104
Voted
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
15 years 2 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
98
Voted
IPPS
2003
IEEE
15 years 3 months ago
Multi-Paradigm Framework for Parallel Image Processing
A software framework for the parallel execution of sequential programs using C++ classes is presented. The functional language Concurrent ML is used to implement the underlying ha...
David J. Johnston, Martin Fleury, Andy C. Downton