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ICECCS
2010
IEEE
196views Hardware» more  ICECCS 2010»
14 years 9 months ago
Implementing and Evaluating a Model Checker for Transactional Memory Systems
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
CODES
1999
IEEE
15 years 1 months ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 6 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
AUTOMATICA
2006
142views more  AUTOMATICA 2006»
14 years 9 months ago
Stability regions in the parameter space: D-decomposition revisited
The challenging problem in linear control theory is to describe the total set of parameters (controller coefficients or plant characteristics) which provide stability of a system....
Elena N. Gryazina, Boris T. Polyak
ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
14 years 1 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...