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» Towards Compilation of Streaming Programs into FPGA Hardware
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CODES
2009
IEEE
15 years 4 months ago
On compile-time evaluation of process partitioning transformations for Kahn process networks
Kahn Process Networks is an appealing model of computation for programming and mapping applications onto multi-processor platforms. Autonomous processes communicate through unboun...
Sjoerd Meijer, Hristo Nikolov, Todor Stefanov
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
15 years 6 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
15 years 1 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
CCS
2008
ACM
14 years 11 months ago
When good instructions go bad: generalizing return-oriented programming to RISC
This paper reconsiders the threat posed by Shacham's "return-oriented programming" -- a technique by which WX-style hardware protections are evaded via carefully cr...
Erik Buchanan, Ryan Roemer, Hovav Shacham, Stefan ...
CASES
2005
ACM
14 years 11 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...