307 search results - page 3 / 62 » Towards Integrated Verification of Timed Transition Models |
ASPDAC
2006
ACM
14 years 12 days ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
TII
2008
13 years 6 months ago
2008
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
FORMATS
2007
Springer
13 years 10 months ago
2007
Springer
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
JUCS
2010
13 years 1 months ago
2010
: There is a need for more rigorous analysis techniques that developers can use for verifying the critical properties in UML models. The UML-based Specification Environment (USE) t...