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» Towards Optimal Bayesian Algorithmic Mechanism Design
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ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
14 years 9 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
104
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AINA
2007
IEEE
15 years 6 months ago
Fuzzy Logic-Based Event Notification in Sparse MANETs
In the Ad-Hoc InfoWare project, we develop a delay tolerant event notification service for sparse Mobile Ad-Hoc Networks for emergency and rescue operations. In most event notific...
Anna K. Lekova, Katrine Stemland Skjelsvik, Thomas...
ICDCS
2009
IEEE
15 years 9 months ago
ISP Friend or Foe? Making P2P Live Streaming ISP-Aware
Abstract: Current peer-to-peer systems are network-agnostic, often generating large volumes of unnecessary inter-ISP traffic. Although recent work has shown the benefits of ISP-a...
Fabio Picconi, Laurent Massoulié
ICCAD
2008
IEEE
89views Hardware» more  ICCAD 2008»
15 years 8 months ago
Temperature aware task sequencing and voltage scaling
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
Ramkumar Jayaseelan, Tulika Mitra
ISPASS
2010
IEEE
15 years 6 months ago
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
After many years of prefetching research, most commercially available systems support only two types of prefetching: software-directed prefetching and hardware-based prefetchers u...
Harold W. Cain, Priya Nagpurkar