Sciweavers

181 search results - page 34 / 37
» Towards a Philosophy of Instruction
Sort
View
80
Voted
IPPS
2006
IEEE
15 years 3 months ago
Compatible phase co-scheduling on a CMP of multi-threaded processors
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya...
77
Voted
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
15 years 3 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
ELPUB
2006
ACM
15 years 3 months ago
Modelling a Layer for Real-Time Management of Interactions in Web Based Distance Learning
In the last few years, the University of Aveiro, Portugal, has been offering several distance learning courses over the Web, using e-learning platforms. Experience showed that dif...
Carlos Sousa Pinto, Fernando M. S. Ramos
RTAS
2005
IEEE
15 years 3 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
SP
2005
IEEE
188views Security Privacy» more  SP 2005»
15 years 3 months ago
BIND: A Fine-Grained Attestation Service for Secure Distributed Systems
In this paper, we propose BIND (Binding Instructions aNd Data),1 a fine-grained attestation service for securing distributed systems. Code attestation has recently received consi...
Elaine Shi, Adrian Perrig, Leendert van Doorn