204 search results - page 34 / 41 » Trace Processors |
113
Voted
PLDI
1995
ACM
15 years 4 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
131
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CHES
2008
Springer
15 years 2 months ago
2008
Springer
Abstract. This paper proposes new chosen-message power-analysis attacks against public-key cryptosystems based on modular exponentiation, which use specific input pairs to generate...
105
Voted
ISCAPDCS
2003
15 years 1 months ago
2003
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
98
Voted
HPDC
2010
IEEE
15 years 1 months ago
2010
IEEE
We introduce LogGOPSim--a fast simulation framework for parallel algorithms at large-scale. LogGOPSim utilizes a slightly extended version of the well-known LogGPS model in combin...
120
Voted
ISLPED
2010
ACM
15 years 19 days ago
2010
ACM
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...