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LCTRTS
2007
Springer
15 years 5 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
147
Voted
SOFTVIS
2010
ACM
14 years 11 months ago
AllocRay: memory allocation visualization for unmanaged languages
A programs memory system performance is one of the key determinants of its overall performance. Lack of understanding of a programs memory system behavior can lead to performance ...
George G. Robertson, Trishul M. Chilimbi, Bongshin...
64
Voted
CVPR
1999
IEEE
16 years 29 days ago
Multiscale Image Registration Using Scale Trace Correlation
This paper presents a method for registering images at different magnifications (scales) by treating the problem not only as one of scaling the image coordinates but also as one i...
Bruce B. Hansen, Bryan S. Morse
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
15 years 3 months ago
Reducing register ports for higher speed and lower energy
The key issues for register file design in high-performance processors are access time and energy. While previous work has focused on reducing the number of registers, we propose...
Il Park, Michael D. Powell, T. N. Vijaykumar
89
Voted
IEEEPACT
1998
IEEE
15 years 3 months ago
Optimistic Register Coalescing
Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important ...
Jinpyo Park, Soo-Mook Moon