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TACAS
2005
Springer
124views Algorithms» more  TACAS 2005»
15 years 4 months ago
Localization and Register Sharing for Predicate Abstraction
ion Himanshu Jain1,2 , Franjo Ivanˇci´c1 , Aarti Gupta1 , and Malay K. Ganai1 1 NEC Laboratories America, Inc., 4 Independence Way, Princeton, NJ 08540 2 School of Computer Scien...
Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay ...
ARCS
2006
Springer
15 years 2 months ago
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
Chen-Yong Cher, Il Park, T. N. Vijaykumar
EMSOFT
2004
Springer
15 years 4 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
PPOPP
1990
ACM
15 years 3 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
VTS
2008
IEEE
78views Hardware» more  VTS 2008»
15 years 5 months ago
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
Trace buffers are commonly used to capture data during in-system silicon debug. This paper exploits the fact that it is not necessary to capture error-free data in the trace buffe...
Joon-Sung Yang, Nur A. Touba