327 search results - page 24 / 66 » Trace register allocation |
ISCA
2002
IEEE
15 years 3 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
MICRO
2008
IEEE
15 years 5 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
110
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JPDC
2010
14 years 9 months ago
2010
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
FPL
2004
Springer
15 years 4 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
184
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ISBI
2011
IEEE
14 years 2 months ago
2011
IEEE
Active research in the area of 3-D neurite tracing has predominantly focused on single sections. Ultimately, however, neurobiologists desire to study the long range connectivity o...