327 search results - page 26 / 66 » Trace register allocation |
ISQED
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—Silicon debug poses a unique challenge to the engineer because of the limited access to internal signals of the chip. Embedded hardware such as trace buffers helps overc...
ISCA
2005
IEEE
15 years 4 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
JUCS
2000
14 years 10 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
IEEEPACT
2005
IEEE
15 years 4 months ago
2005
IEEE
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
— In this paper, we present a two-pass error-resilience transcoding scheme based on content-aware intra-refresh (CAIR) for inserting error-resilience features to a compressed vid...