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CASES
2009
ACM
14 years 8 months ago
Spatial complexity of reversibly computable DAG
In this paper we address the issue of making a program reversible in terms of spatial complexity. Spatial complexity is the amount of memory/register locations required for perfor...
Mouad Bahi, Christine Eisenbeis
DATE
2009
IEEE
125views Hardware» more  DATE 2009»
15 years 5 months ago
HLS-l: High-level synthesis of high performance latch-based circuits
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
Seungwhun Paik, Insup Shin, Youngsoo Shin
PLDI
2003
ACM
15 years 4 months ago
Static array storage optimization in MATLAB
An adaptation of the classic register allocation algorithm to the problem of array storage optimization in MATLAB is presented. The method involves the decomposition of an interfe...
Pramod G. Joisha, Prithviraj Banerjee
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
15 years 5 months ago
Cooptimization of interface hardware and software for I/O controllers
The allocation of device variables on I/O registers affects the code size and performance of an I/O device driver. This work seeks the allocation with the minimal software or hard...
Kuan Jen Lin, Shih Hao Huang, Shan Chien Fang
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
15 years 3 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik