327 search results - page 52 / 66 » Trace register allocation |
77
Voted
HPCC
2009
Springer
15 years 3 months ago
2009
Springer
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
104
Voted
ASPDAC
1998
ACM
15 years 3 months ago
1998
ACM
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
IWMM
1998
Springer
15 years 3 months ago
1998
Springer
Stoye's one-bit reference tagging scheme can be extended to local counts of two or more via two strategies. The first, suited to pure register transactions, is a cache of ref...
92
Voted
ICALP
1990
Springer
15 years 3 months ago
1990
Springer
Any tree can be represented in a max/ma//y compact form as a directed acyclic graph where common subtrees are factored and shared, being represented only once. Such a compaction ca...
CODES
2004
IEEE
15 years 2 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...