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73
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IJPP
2006
82views more  IJPP 2006»
14 years 11 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
TVLSI
2008
120views more  TVLSI 2008»
14 years 10 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
89
Voted
LCPC
2005
Springer
15 years 4 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
KDD
2010
ACM
247views Data Mining» more  KDD 2010»
15 years 27 days ago
Metric forensics: a multi-level approach for mining volatile graphs
Advances in data collection and storage capacity have made it increasingly possible to collect highly volatile graph data for analysis. Existing graph analysis techniques are not ...
Keith Henderson, Tina Eliassi-Rad, Christos Falout...
105
Voted
SIGMETRICS
2005
ACM
105views Hardware» more  SIGMETRICS 2005»
15 years 4 months ago
An interposed 2-Level I/O scheduling framework for performance virtualization
I/O consolidation is a growing trend in production environments due to the increasing complexity in tuning and managing storage systems. A consequence of this trend is the need to...
Jianyong Zhang, Anand Sivasubramaniam, Alma Riska,...