Sciweavers

327 search results - page 61 / 66
» Trace register allocation
Sort
View
DAC
2005
ACM
16 years 5 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
MICCAI
2006
Springer
16 years 5 months ago
A Learning Based Algorithm for Automatic Extraction of the Cortical Sulci
This paper presents a learning based method for automatic extraction of the major cortical sulci from MRI volumes or extracted surfaces. Instead of using a few pre-defined rules su...
Songfeng Zheng, Zhuowen Tu, Alan L. Yuille, Allan ...
MOBISYS
2008
ACM
16 years 4 months ago
Cascadia: a system for specifying, detecting, and managing rfid events
Cascadia is a system that provides RFID-based pervasive computing applications with an infrastructure for specifying, extracting and managing meaningful high-level events from raw...
Evan Welbourne, Nodira Khoussainova, Julie Letchne...
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
15 years 11 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
AFRICACRYPT
2010
Springer
15 years 7 months ago
Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator
Abstract. This article investigates the relevance of the theoretical framework on profiled side-channel attacks presented by F.-X. Standaert et al. at Eurocrypt 2009. The analyses ...
M. Abdelaziz Elaabid, Sylvain Guilley