638 search results - page 19 / 128 » Track Layouts of Graphs |
74
Voted
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
FAW
2009
Springer
15 years 4 months ago
2009
Springer
Data access time becomes the main bottleneck in applications dealing with large-scale graphs. Cache-oblivious layouts, constructed to minimize the geometric mean of arc lengths of ...
JGAA
2002
14 years 9 months ago
2002
Enabling the user of a graph drawing system to preserve the mental map between two different layouts of a graph is a major problem. In this paper we present methods that smoothly ...
GD
2009
Springer
15 years 2 months ago
2009
Springer
Recently, we have presented a new practical method for upward crossing minimization [4], which clearly outperformed existing approaches for drawing hierarchical graphs in that resp...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
––This paper describes algorithms for automatic layout synthesisofleafcellsin1–dandinanew1–1/2–dlayoutstyle,useful for non–dual circuit styles. The graph theory based a...