638 search results - page 23 / 128 » Track Layouts of Graphs |
ASPDAC
1998
ACM
15 years 1 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
CAIP
2009
Springer
15 years 1 months ago
2009
Springer
Abstract. In this paper we propose a new approach to improve electronic editions of literary corpus, providing an efficient estimation of manuscripts pages structure. In any handwr...
76
Voted
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module...
129
Voted
TCAD
2010
14 years 4 months ago
2010
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
GD
2000
Springer
15 years 1 months ago
2000
Springer
We present a multi-scale layout algorithm for the aesthetic drawing of undirected graphs with straight-line edges. The algorithm is extremely fast, and is capable of drawing graph...