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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 4 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
INFOCOM
1998
IEEE
15 years 4 months ago
Performance Bounds for Dynamic Channel Assignment Schemes Operating under Varying Re-Use Constraints
-We derive bounds for the performance of dynamic channel assignment (DCA) schemeswhich strengthenthe existing Erlang bound. The construction of the bounds is based on a reward para...
Philip A. Whiting, Sem C. Borst
ICCAD
2008
IEEE
99views Hardware» more  ICCAD 2008»
15 years 8 months ago
Evaluation of voltage interpolation to address process variations
Abstract— Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. ...
Kevin Brownell, Gu-Yeon Wei, David Brooks
ASAP
2010
IEEE
143views Hardware» more  ASAP 2010»
15 years 1 months ago
Loop transformations for interface-based hierarchies IN SDF graphs
Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data...
Jonathan Piat, Shuvra S. Bhattacharyya, Mickaë...
MOZ
2004
Springer
15 years 5 months ago
A Mozart Implementation of CP(BioNet)
The analysis of biochemical networks consists in studying the interactions between biological entities cooperating in complex cellular processes. To facilitate the expression of an...
Grégoire Dooms, Yves Deville, Pierre Dupont