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ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
14 years 19 days ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
DAC
2011
ACM
12 years 6 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 19 days ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
HPCA
2009
IEEE
14 years 6 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
SIGMETRICS
2004
ACM
105views Hardware» more  SIGMETRICS 2004»
13 years 11 months ago
A model of BGP routing for network engineering
The performance of IP networks depends on a wide variety of dynamic conditions. Traffic shifts, equipment failures, planned maintenance, and topology changes in other parts of th...
Nick Feamster, Jared Winick, Jennifer Rexford