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ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
15 years 6 months ago
Requirements and Concepts for Transaction Level Assertions
— The latest development of hardware design and ation methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction l...
Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas ...
TECS
2008
122views more  TECS 2008»
14 years 9 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 2 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
SIGMETRICS
2008
ACM
130views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
Using probabilistic model checking in systems biology
Probabilistic model checking is a formal verification framework for systems which exhibit stochastic behaviour. It has been successfully applied to a wide range of domains, includ...
Marta Z. Kwiatkowska, Gethin Norman, David Parker
CSFW
2010
IEEE
15 years 29 days ago
Formal Verification of Privacy for RFID Systems
RFID tags are being widely employed in a variety of applications, ranging from barcode replacement to electronic passports. Their extensive use, however, in combination with their ...
Mayla Brusò, Konstantinos Chatzikokolakis, ...