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ICCAD
1998
IEEE
82views Hardware» more  ICCAD 1998»
15 years 1 months ago
Symbolic model checking of process networks using interval diagram techniques
In this paper, an approach to symbolic model checking of process networks is introduced. It is based on interval decision diagrams (IDDs), a representation of multi-valued functio...
Karsten Strehl, Lothar Thiele
84
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DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 1 months ago
Formal Refinement and Model Checking of an Echo Cancellation Unit
This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML sta...
Alexander Krupp, Wolfgang Müller 0003, Ian Ol...
76
Voted
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
15 years 2 months ago
FunState - an internal design representation for codesign
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components a...
Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Ro...
TCAD
2002
146views more  TCAD 2002»
14 years 9 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
CAV
2008
Springer
96views Hardware» more  CAV 2008»
14 years 11 months ago
Implied Set Closure and Its Application to Memory Consistency Verification
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...
Surender Baswana, Shashank K. Mehta, Vishal Powar