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DATE
2003
IEEE
134views Hardware» more  DATE 2003»
15 years 3 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
CL
2008
Springer
14 years 9 months ago
Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...
Pao-Ann Hsiung, Shang-Wei Lin
DAC
2005
ACM
15 years 10 months ago
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubn...
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
15 years 4 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
68
Voted
AAAI
2004
14 years 11 months ago
Model Checking Temporal Logics of Knowledge in Distributed Systems
Model checking is a promising approach to automatic verification, which has concentrated on specification expressed in temporal logic. Comparatively little attention has been give...
Kaile Su