372 search results - page 50 / 75 » Transaction Based Modeling and Verification of Hardware Prot... |
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distributed embedded systems. The communication model is based on...
ISPASS
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
106
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ASPDAC
2010
ACM
14 years 7 months ago
2010
ACM
Abstract-- We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based on optimized computation and contention-free routing. Th...
103
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ENTCS
2006
14 years 9 months ago
2006
Bounded Model Checking (BMC) searches for counterexamples to a property with a bounded length k. If no such counterexample is found, k is increased. This process terminates when ...