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APCSAC
2007
IEEE
15 years 6 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
RTCSA
2007
IEEE
15 years 6 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
CAL
2008
14 years 10 months ago
Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. Howev...
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, ...
HASE
2008
IEEE
15 years 6 months ago
Small Logs for Transactional Services: Distinction is Much More Accurate than (Positive) Discrimination
For complex services, logging is an integral part of many middleware aspects, especially, transactions and monitoring. In the event of a failure, the log allows us to deduce the c...
Debmalya Biswas, Thomas Gazagnaire, Blaise Genest
IJISEC
2006
106views more  IJISEC 2006»
14 years 11 months ago
Execution transactions for defending against software failures: use and evaluation
We examine the problem of containing buffer overflow attacks in a safe and efficient manner. Briefly, we automatically augment source code to dynamically catch stack and heap-based...
Stelios Sidiroglou, Angelos D. Keromytis