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APCSAC
2007
IEEE
15 years 4 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
RTCSA
2007
IEEE
15 years 3 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
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CAL
2008
14 years 8 months ago
Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. Howev...
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, ...
ICAC
2006
IEEE
15 years 3 months ago
Utility-aware Resource Allocation in an Event Processing System
— Event processing systems link event producers and consumers in a flexible manner, by supporting multiple communication patterns and powerful message transformations. Such syst...
Sumeer Bhola, Mark Astley, Robert Saccone, Michael...
IJISEC
2006
106views more  IJISEC 2006»
14 years 9 months ago
Execution transactions for defending against software failures: use and evaluation
We examine the problem of containing buffer overflow attacks in a safe and efficient manner. Briefly, we automatically augment source code to dynamically catch stack and heap-based...
Stelios Sidiroglou, Angelos D. Keromytis