We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
We consider unranked trees, that have become an active subject of study recently due to XML applications, and characterize commonly used fragments of firstorder (FO) and monadic ...
Abstract. We consider the problem of specifying and computing consistent answers to queries against databases that do not satisfy given integrity constraints. This is done by simul...
Marcelo Arenas, Leopoldo E. Bertossi, Michael Kife...
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...