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ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
15 years 3 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
EGC
2005
Springer
15 years 3 months ago
Transparent Fault Tolerance for Grid Applications
A major challenge facing grid applications is the appropriate handling of failures. In this paper we address the problem of making parallel Java applications based on Remote Method...
Pawel Garbacki, Bartosz Biskupski, Henri E. Bal
ESTIMEDIA
2005
Springer
15 years 3 months ago
Custom Processor Design Using NISC: A Case-Study on DCT algorithm
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
Bita Gorjiara, Daniel D. Gajski
EUC
2005
Springer
15 years 3 months ago
Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs
Abstract. Loop distribution and loop fusion are two effective loop transformation techniques to optimize the execution of the programs in DSP applications. In this paper, we propo...
Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, M...
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 3 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...