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» Transistor-Level Timing Analysis Using Embedded Simulation
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163
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ISI
2006
Springer
15 years 2 months ago
An Embedded Bayesian Network Hidden Markov Model for Digital Forensics
In the paper we combine a Bayesian Network model for encoding forensic evidence during a given time interval with a Hidden Markov Model (EBN-HMM) for tracking and predicting the de...
Olivier Y. de Vel, Nianjun Liu, Terry Caelli, Tib&...
142
Voted
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
15 years 8 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
135
Voted
RTCSA
2005
IEEE
15 years 8 months ago
Scheduling Support for Guaranteed Time Services in IEEE 802.15.4 Low Rate WPAN
We propose a real-time message scheduling algorithm which is applied to schedule periodic realtime messages in IEEE 802.15.4 for LR-WPAN(Low Rate Wireless Personal Area Network). ...
Seongeun Yoo, Daeyoung Kim, Minh-Long Pham, Yoonme...
105
Voted
SAC
2004
ACM
15 years 8 months ago
Using semi-lagrangian formulations with automatic code generation for environmental modeling
An import issue for numerical weather prediction modes (NWP) is the time it takes to produce a valid forecast. One factor, which greatly influences this simulation time is the si...
Paul van der Mark, Lex Wolters, Gerard Cats
129
Voted
CASES
2006
ACM
15 years 8 months ago
Code transformation strategies for extensible embedded processors
Embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. I...
Paolo Bonzini, Laura Pozzi