1640 search results - page 137 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
125
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WCET
2010
15 years 1 months ago
2010
Calculating the worst-case execution time (WCET) of real-time tasks is still a tedious job. Programmers are required to provide additional information on the program flow, analyzi...
134
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SIGMETRICS
2004
ACM
15 years 8 months ago
2004
ACM
The Least Attained Service (LAS) scheduling policy, when used for scheduling packets over the bottleneck link of an Internet path, can greatly reduce the average flow time for sh...
102
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DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
121
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DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
This paper introduces a method and tool-support for the automatic analysis and verification of hybrid and embedded control systems, whose continuous dynamics are often modelled u...
130
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GLOBECOM
2007
IEEE
15 years 9 months ago
2007
IEEE
Abstract— In this paper, we answer the question that “Can conventional differential unitary space time modulation (DUSTM) be applied when there is an unknown carrier frequency ...