1640 search results - page 143 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
114
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CODES
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft c...
143
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ENTCS
2007
15 years 3 months ago
2007
This paper gives an overview of recent advances in Real-Time Maude. Real-Time Maude extends the Maude rewriting logic tool to support formal specification and analysis of object-...
168
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ECRTS
2006
IEEE
15 years 9 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
123
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ATAL
2010
Springer
15 years 4 months ago
2010
Springer
Experimental analysis of networks of cooperative learning agents (to verify certain properties such as the system's stability) has been commonly used due to the complexity of...
138
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ICICS
2004
Springer
15 years 8 months ago
2004
Springer
Abstract. The NRL Pump protocol defines a multilevel secure component whose goal is to minimize leaks of information from high level systems to lower level systems, without degrad...