1640 search results - page 157 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
168
Voted
JCM
2008
15 years 3 months ago
2008
In this paper, we present a new simulation platform for complex, radio standard spanning mobile Ad Hoc networks. SimANet - Simulation Platform for Ambient Networks - allows the coe...
140
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RTAS
2005
IEEE
15 years 9 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
148
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VALUETOOLS
2006
ACM
15 years 9 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
132
Voted
RTCSA
2005
IEEE
15 years 9 months ago
2005
IEEE
This paper describes a context information acquisition framework for a personal device that equips a variety of sensors. The framework captures context information about a user an...
121
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CPHYSICS
2004
15 years 3 months ago
2004
We introduce here a new method for the numerical resolution of the Vlasov equation on a phase space grid using an adaptive semi-Lagrangian method. The adaptivity is obtained throu...