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» Transistor-Level Timing Analysis Using Embedded Simulation
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130
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CORR
2008
Springer
104views Education» more  CORR 2008»
15 years 3 months ago
Policies of System Level Pipeline Modeling
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...
Edwin A. Harcourt
GECCO
2006
Springer
162views Optimization» more  GECCO 2006»
15 years 7 months ago
Improving evolutionary real-time testing
Embedded systems are often used in a safety-critical context, e.g. in airborne or vehicle systems. Typically, timing constraints must be satisfied so that real-time embedded syste...
Marouane Tlili, Stefan Wappler, Harmen Sthamer
168
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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 3 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
128
Voted
ICC
2007
IEEE
170views Communications» more  ICC 2007»
15 years 9 months ago
A Post-Detection SNR-Aided Timing Recovery Loop for MIMO-OFDM Receivers
--- In this paper, a novel third-order Phase Lock Loop (PLL) is proposed for the timing recovery in MIMO-OFDM systems. It differentiates from conventional timing recovery algorithm...
Wenzhen Li, Masayuki Tomisawa
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 8 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang