1640 search results - page 164 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
119
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STTT
1998
15 years 3 months ago
1998
Abstract. Coloured Petri nets (CP-nets or CPNs) provide a framework for the design, specification, validation, and verification of systems. CP-nets have a wide range of applicati...
155
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IEEEHPCS
2010
15 years 1 months ago
2010
In grid computing systems, providing fault-tolerance is required for both scientific computation and file-sharing to increase their reliability. In previous works, several mechani...
134
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ICCD
2004
IEEE
16 years 9 days ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
152
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DATE
2010
IEEE
15 years 8 months ago
2010
IEEE
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
136
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PETRA
2009
ACM
15 years 10 months ago
2009
ACM
We propose a system to identify people in a sensor network. The system fuses motion information measured from wearable accelerometer nodes with motion traces of each person detect...