1640 search results - page 173 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
134
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DAC
2005
ACM
15 years 5 months ago
2005
ACM
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
125
Voted
DAC
2004
ACM
16 years 4 months ago
2004
ACM
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
132
Voted
GECCO
2007
Springer
15 years 9 months ago
2007
Springer
Design, development and evaluation of adaptive, scalable, and power aware Bio/Nature inspired routing protocols has received a significant amount of attention in the recent past....
134
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FDL
2006
IEEE
15 years 9 months ago
2006
IEEE
Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
124
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FASE
2004
Springer
15 years 7 months ago
2004
Springer
We present a formal operational semantics for Stateflow, the graphical Statecharts-like language of the Matlab/Simulink tool suite that is widely used in model-based development of...