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» Transistor-Level Timing Analysis Using Embedded Simulation
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WMPI
2004
ACM
15 years 8 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...
TASLP
2010
99views more  TASLP 2010»
15 years 1 months ago
A Virtual Model of Spring Reverberation
—The digital emulation of analog audio effects and synthesis components, through the simulation of lumped circuit components has seen a large amount of activity in recent years; ...
Stefan Bilbao, Julian Parker
TMC
2010
230views more  TMC 2010»
15 years 1 months ago
Bandwidth Recycling in IEEE 802.16 Networks
—IEEE 802.16 standard was designed to support the bandwidth demanding applications with quality of service (QoS). Bandwidth is reserved for each application to ensure the QoS. Fo...
D. Chuck, J. M. Chang
ICDCSW
2003
IEEE
15 years 8 months ago
IEEE 802.11 Ad Hoc Networks: Performance Measurements
 In this paper we investigate the performance of IEEE 802.11 ad hoc networks by means of an experimental study. Measurements on IEEE 802.11 ad hoc networks confirm previous sim...
Giuseppe Anastasi, Eleonora Borgia, Marco Conti, E...
IPPS
2009
IEEE
15 years 10 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...