1640 search results - page 193 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
168
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WORDS
2005
IEEE
15 years 8 months ago
2005
IEEE
Since the deployment of real-time sensitive applications in the Internet, the research community has been struggling to leverage the IP best-effort networks for providing QoS assu...
123
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ICA3PP
2009
Springer
15 years 7 months ago
2009
Springer
Stereoscopic scenes of the mankind is naturally caused by synthesizing two images produced by the parallax of the two eyes of human. Such being the case, mankind can distinguish t...
107
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DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
223
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DAC
2011
ACM
14 years 3 months ago
2011
ACM
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
119
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ICRA
2007
IEEE
15 years 9 months ago
2007
IEEE
— In this paper we present an observability analysis for a mobile robot performing SLAM with a single monocular camera. The aim is to get a better understanding of the well known...