1640 search results - page 239 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
124
Voted
TCAD
2002
15 years 2 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
111
Voted
IJHCI
2010
15 years 1 months ago
2010
Motivation – Investigations of large-scale outages in the North American interconnected electric system often attribute the causes to three T’s: Trees, Training and Tools. To ...
129
Voted
ISPDC
2010
IEEE
15 years 1 months ago
2010
IEEE
—In this paper, we propose SKAIT, a parameterized symmetric key pre-distribution scheme that guarantees a secure and confidential channel between every pair of nodes in a wirele...
110
Voted
ICRA
2006
IEEE
15 years 8 months ago
2006
IEEE
— In this paper, we study the problem of localization using relative-state estimates. It is shown, that when the same exteroceptive sensor measurement is processed for the comput...
135
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ANCS
2005
ACM
15 years 8 months ago
2005
ACM
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first pro...