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» Transistor-Level Timing Analysis Using Embedded Simulation
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154
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DAC
2005
ACM
16 years 3 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
149
Voted
FORMATS
2007
Springer
15 years 6 months ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
132
Voted
INFOCOM
1996
IEEE
15 years 7 months ago
Integrated Control of Connection Admission, Flow Rate, and Bandwidth for ATM Based Networks
: We consider the combined control problem of connection admission, flow rate, and bandwidth allocation (capacity, service-rate) under nonstationary conditions. A fluid flow model ...
Andreas Pitsillides, Petros A. Ioannou, David Tipp...
133
Voted
INFOCOM
1998
IEEE
15 years 7 months ago
Timer Reconsideration for Enhanced RTP Scalability
RTP, the Real Time Transport Protocol, has gained widespread acceptance as the transport protocol for voice and video on the Internet. Its companion control protocol, the Real Tim...
Jonathan Rosenberg, Henning Schulzrinne
111
Voted
SDM
2009
SIAM
152views Data Mining» more  SDM 2009»
15 years 12 months ago
Non-negative Matrix Factorization, Convexity and Isometry.
In this paper we explore avenues for improving the reliability of dimensionality reduction methods such as Non-Negative Matrix Factorization (NMF) as interpretive exploratory data...
Nikolaos Vasiloglou, Alexander G. Gray, David V. A...