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» Transistor-Level Timing Analysis Using Embedded Simulation
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133
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RTAS
2007
IEEE
15 years 9 months ago
Full Duplex Switched Ethernet for Next Generation "1553B"-Based Applications
Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and c...
Ahlem Mifdaoui, Fabrice Frances, Christian Fraboul
133
Voted
BMCBI
2007
176views more  BMCBI 2007»
15 years 2 months ago
Correlation-maximizing surrogate gene space for visual mining of gene expression patterns in developing barley endosperm tissue
Background: Micro- and macroarray technologies help acquire thousands of gene expression patterns covering important biological processes during plant ontogeny. Particularly, fait...
Marc Strickert, Nese Sreenivasulu, Björn Usad...
141
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TCS
2002
15 years 2 months ago
Specification of real-time and hybrid systems in rewriting logic
This paper explores the application of rewriting logic to the executable formal modeling of real-time and hybrid systems. We give general techniques by which such systems can be s...
Peter Csaba Ölveczky, José Meseguer
139
Voted
ICCV
2003
IEEE
16 years 4 months ago
Graph Partition by Swendsen-Wang Cuts
Vision tasks, such as segmentation, grouping, recognition, can be formulated as graph partition problems. The recent literature witnessed two popular graph cut algorithms: the Ncu...
Adrian Barbu, Song Chun Zhu
138
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ADBIS
2006
Springer
93views Database» more  ADBIS 2006»
15 years 8 months ago
An On-Line Reorganization Framework for SAN File Systems
While the cost per megabyte of magnetic disk storage is economical, organizations are alarmed by the increasing cost of managing storage. Storage Area Network (SAN) architectures ...
Shahram Ghandeharizadeh, Shan Gao, Chris Gahagan, ...