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» Transistor-Level Timing Analysis Using Embedded Simulation
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173
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DAC
2006
ACM
16 years 3 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
ASIASIM
2004
Springer
15 years 8 months ago
Design and Implementation of an SSL Component Based on CBD
Abstract. SSL is one of the most popular protocols used on the Internet for secure communications. However SSL protocol has several problems. First, SSL protocol brings considerabl...
Eun-Ae Cho, Young-Gab Kim, Chang-Joo Moon, Doo-Kwo...
126
Voted
CEC
2009
IEEE
15 years 9 months ago
Evolving morphology and control: A distributed approach
—In this paper we present a model which allows to co-evolve the morphology and the control system of realistically simulated robots (creatures). The method proposed is based on a...
Mariagiovanna Mazzapioda, Angelo Cangelosi, Stefan...
119
Voted
JUCS
2006
112views more  JUCS 2006»
15 years 2 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ITC
2003
IEEE
139views Hardware» more  ITC 2003»
15 years 7 months ago
Fault Pattern Oriented Defect Diagnosis for Memories
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experi...
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung...