1640 search results - page 263 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
89
Voted
DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
135
Voted
GLOBECOM
2006
IEEE
15 years 8 months ago
2006
IEEE
In most of the proposed clustering algorithms for wireless ad hoc networks, the cluster-heads form a dominating set in the network topology. A variant of dominating set which is mo...
ISPA
2005
Springer
15 years 8 months ago
2005
Springer
In this paper, we propose efficient routing algorithms for 2D torus with possible large number of faulty nodes. There is no presumption on the number and the distribution of faulty...
ISCAS
2002
IEEE
15 years 7 months ago
2002
IEEE
In this paper, an analog implementation of the Wavelet Transform (WT) is presented. The circuit is based on the Dynamic Translinear (DTL) circuit technique and implements, by mean...
111
Voted
APCCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...