1640 search results - page 274 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
130
Voted
ITNG
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
105
Voted
TRIDENTCOM
2008
IEEE
15 years 9 months ago
2008
IEEE
— Wireless reprogramming of the sensor network is useful for uploading new code or for changing the functionality of the existing code. In recent years, the research focus has sh...
106
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ASPDAC
2006
ACM
15 years 8 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
DAC
1997
ACM
15 years 6 months ago
1997
ACM
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
103
Voted
DAC
2009
ACM
15 years 9 months ago
2009
ACM
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increas...