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» Transistor-Level Timing Analysis Using Embedded Simulation
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NLE
2008
140views more  NLE 2008»
15 years 2 months ago
Active learning and logarithmic opinion pools for HPSG parse selection
For complex tasks such as parse selection, the creation of labelled training sets can be extremely costly. Resource-efficient schemes for creating informative labelled material mu...
Jason Baldridge, Miles Osborne
IISWC
2006
IEEE
15 years 8 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
DAC
2008
ACM
15 years 4 months ago
IntellBatt: towards smarter battery design
Battery lifetime and safety are primary concerns in the design of battery operated systems. Lifetime management is typically supervised by the system via battery-aware task schedu...
Suman Kalyan Mandal, Praveen Bhojwani, Saraju P. M...
HPCA
2009
IEEE
16 years 3 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
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INFOCOM
2007
IEEE
15 years 8 months ago
Face Tracing Based Geographic Routing in Nonplanar Wireless Networks
— Scalable and efficient routing is a main challenge in the deployment of large ad hoc wireless networks. An essential element of practical routing protocols is their accommodat...
Fenghui Zhang, Hao Li, Anxiao Jiang, Jianer Chen, ...