1640 search results - page 36 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
104
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CODES
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper presents an RTOS-centric hardwareisoftware cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is tha...
108
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DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clock...
132
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IESS
2007
Springer
15 years 8 months ago
2007
Springer
: The performance of feasibility tests is crucial in many applications. When using feasibility tests online only a limited amount of analysis time is available. Run-time efficiency...
104
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ICCAD
2005
IEEE
15 years 11 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
128
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ATVA
2009
Springer
15 years 6 months ago
2009
Springer
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...