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» Transistor-Level Timing Analysis Using Embedded Simulation
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WCET
2007
15 years 3 months ago
Automatic Amortised Worst-Case Execution Time Analysis
Our research focuses on formally bounded WCET analysis, where we aim to provide absolute guarantees on execution time bounds. In this paper, we describe how amortisation can be us...
Christoph A. Herrmann, Armelle Bonenfant, Kevin Ha...
RTSS
2007
IEEE
15 years 8 months ago
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
In the last years, a progressive migration from single processor chips to multi-core computing devices has taken place in the general-purpose and embedded system market. The devel...
Marko Bertogna, Michele Cirinei
RTAS
2003
IEEE
15 years 7 months ago
Analysis of the Execution Time Unpredictability caused by Dynamic Branch Prediction
This paper investigates how dynamic branch prediction in a microprocessor affects the predictability of execution time for software running on that processor. By means of experim...
Jakob Engblom
ESANN
2006
15 years 3 months ago
Lag selection for regression models using high-dimensional mutual information
Mutual information may be used to select the embedding lag of a time series. However, this lag selection is usually limited to the analysis of the mutual information between a pair...
Geoffroy Simon, Michel Verleysen
112
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RTCSA
2005
IEEE
15 years 8 months ago
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing st...
Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, We...